Electronic matrix arrays find considerable application in X-ray image sensors. Such devices generally include X and Y (or row and column) address lines which are horizontally and vertically spaced apart and cross at an angle to one another thereby forming a plurality of crossover points. Associated with each crossover point is an element (e.g. pixel) to be selectively addressed. These elements in many instances are memory cells or pixels of an electronically adjustable memory array or imager array.
Typically, a switching or isolation device(s) such as a diode or thin film transistor (TFT) is associated with each array element or pixel. The isolation devices permit the individual pixels to be selectively addressed.
Amorphous silicon (a-Si) TFTs have found wide usage for isolation devices. Structurally, TFTs generally include substantially co-planar source and drain electrodes, a thin film semiconductor material (e.g. a-Si) disposed between the source and drain electrodes, and a gate electrode in proximity to the semiconductor but electrically insulated therefrom by a gate insulator. Current flow through the TFT between the source and drain is controlled by the application of voltage to the gate electrode. The voltage to the gate electrode produces an electric field which accumulates a charged region near the semiconductor-gate insulator interface. This charged region forms a current conducting channel in the semiconductor through which current is conducted. Thus, by controlling the voltage to the gate one may read or detect the charge detected by a storage capacitor or photodiode in a corresponding imager pixel. Herein, the TFT electrode which is connected to the collector electrode is known as the "source."
Imagers including arrays of pixels are known in the art. For example, see U.S. Pat. Nos. 5,498,880; 5,396,072; 5,079,426; 4,672,454; and 5,381,014, the disclosures of which are incorporated herein by reference. For example, U.S. Pat. No. 5,381,014 discloses an X-ray imager including an array of pixels where each pixel includes a switching thin film transistor (TFT) and a storage capacitor. Over top of the TFTs and storage capacitors, a charge blocking barrier layer of aluminum oxide is provided in order to prevent charge leakage from the overlying photoconductive layer.
Alternatively, it is known to use an etchable silicon oxide barrier layer to prevent charge leakage, and to deposit such a layer via sputtering.
Unfortunately, the use of the aforesaid materials for the interface barrier layer is problematic for at least the following reasons. The processing steps to deposit and pattern such material(s) are burdensome and overly complicated. For example, cumbersome masks are often required for the sputtering deposition required for these materials in order to prevent bond pads from being coated. These masks are undesirable. Also, the potential resist coating and etching required to pattern such materials is undesirable and requires many more process/manufacturing steps that would otherwise be desirable.
It is apparent from the above that there exists a need in the art for an improved method for manufacturing a large area radiation imager, and for a corresponding imager, including a reduced number of processing/manufacturing steps being required to make the product, and an efficient charge carrier blocking material being used.
It is a purpose of this invention to fulfill the above-described needs in the art, as well as other needs which will become apparent to the skilled artisan from the following detailed description of this invention.